1. Field of the Invention
The present invention relates to a phase locked loop with a controllable oscillator for generating an output signal of the phase locked loop and with a switch-over device for switching over between a first clock signal and a second clock signal for use as the input clock signal of the phase locked loop.
Further, the invention relates to a method for the operation of a phase locked loop, wherein a controllable oscillator generates an output signal of the phase locked loop and can be switched over between a first clock signal and a second clock signal for use as the input clock signal of the phase locked loop.
2. Description of the Prior Art
Such a phase locked loop, referred to in short hereinafter as “PLL”, and such an operating method for a PLL are known for example from U.S. Pat. No. 6,741,109.
Quite generally, a PLL serves to synchronise a controllable oscillator, which generates an output signal with an output frequency, by means of a feedback with an input clock signal with an input frequency. For this purpose, the PLL comprises a phase detector or phase comparator, at the input whereof the input clock signal and the PLL output signal are present. A signal representing the phase difference between these two signals is usually used to control the oscillator via an active or passive, digital or analog filter (“loop filter”).
The areas of application of PLL switching circuits are diverse. For example, PLLs can be used for clock recovery from digital signal sequences or FM demodulation. In communication standards such as “SONET” and “SDH”, clock generation circuits are required for generating clock signals when sending and receiving data. In such a circuit, a PLL circuit can generate, e.g. from an input clock signal inputted as a reference, one or more output clock signals for use in a communication system. The synchronisation of the PLL output signal to an input clock signal does not necessarily mean here that the frequencies of these two signals are identical. On the contrary, a more or less arbitrary frequency ratio can be provided in a manner known per se by means of an arrangement of frequency dividers at the input and/or at the output and/or in the feedback path of the PLL circuit.
The present invention, as also the aforementioned U.S. Pat. No. 6,741,109, proceeds from the fact that, in such a PLL, it is possible to switch between a first clock signal and a second clock signal for use as an input clock signal of the PLL. This in no way rules out the fact that more than two clock signals can be used as an input clock signal of the PLL. On the contrary, it is essential that, from a number of clock signals, only one clock signal is always selected and actually used to generate the PLL output signal. The provision of a number of clock signals may be advantageous in particular to create a redundancy in a communication system. If, for example, one of the clock signals serving as a reference “gets lost”, a switch-over to another clock signal for use as an input clock signal of the PLL can take place in the PLL circuit of the clock generation circuit. Especially for the use of the PLL in communication systems for clock generation or clock recovery, it is desirable here that no significant phase change (“phase hit”) takes place in the PLL output signal due to such a switch-over procedure. Such a phase change can however occur if the first and second clock signals possess different phases immediately before the switch-over.
A known possibility of avoiding abrupt phase changes as a result of a switch-over procedure consists in selecting the PLL bandwidth (“loop gain”) very small (for the aforementioned communication systems, for example, in the order of magnitude of several Hz). In this case, the phase of the PLL output signal changes only very slowly, even if the clock signals between which switching-over takes place have a relatively large phase difference immediately before the switch-over. No data transfer errors then occur in the mentioned communication systems. This solution, however, has in particular the following two drawbacks: on the one hand, a particularly small PLL bandwidth is difficult to produce in an integrated circuit arrangement. On the other hand, a disadvantageously smaller capture range of the PLL also results from a small PLL bandwidth. The PLL capture range may for example be less than 1 ppm for a PLL bandwidth of several Hz.
In order to avoid phase changes of the PLL output signal due to a switch-over procedure and in order to guarantee “hitless switching”, it is proposed in the aforementioned U.S. Pat. No. 6,741,109 that, for the clock signal currently not being used to generate the output signal, the phase difference of said clock signal with respect to a feedback signal derived from the PLL output signal is ascertained and stored. When a switch-over to this clock signal takes place, the stored phase difference is injected at a suitable point into the PLL in order to compensate for the phase difference. With this solution, the accuracy of the compensation achievable in practice and the circuit outlay required for the compensation is problematic.
Irrespective of this, it is problematic with the known solution if the clock signals between which the switch-over is to take place have frequencies that differ significantly from one another. In the case of such a frequency difference, it would be desirable for the oscillation frequency of the oscillator to change correspondingly “immediately” or abruptly when the switch-over takes place. The known solution based on an “observation of the phase difference” is not however capable of achieving this, since the information concerning the phase difference between two signals existing at a specific time does not possess any informative value concerning a frequency difference that may exist between these signals. When a switch-over takes place between two clock signals with a frequency differing from one another, the PLL output signal will ultimately adjust to the frequency of the currently used clock signal, but this adjustment requires a more or less long time, which is not available for many areas of application.